(a) Field of the Invention
The present invention relates to a multi-layer interconnection structure in a semiconductor device and a method for fabricating the same, and more in detail, to the multi-layer interconnection structure including a plurality of interconnects having different interconnect film thicknesses in a single interconnect layer in which a parasitic capacitance and a parasitic resistance can be best established depending on demands on a circuit operation and an interconnect length, and the method for fabricating the same.
(b) Description of the Related Art
With higher integration and miniaturization of a semiconductor device, interconnects for connecting respective regions of a semiconductor element are multi-layer to reduce a surface area required for interconnects in the interconnect design of the semiconductor device because miniaturization of the respective semiconductor elements are more and more requested.
The semiconductor device is configured as a large-scale integrated circuit having a significant number of electronic circuits including semiconductor elements having a variety of functions.
The interconnects of the semiconductor device are composed as a collective member for connecting the respective semiconductor elements. The interconnects include a long-distance interconnect for connecting the semiconductor elements disposed relatively far from each other, a medium-distance interconnect for connecting those disposed in a relatively short distance and a short-distance interconnect for connecting regions in a single semiconductor element.
The interconnects in the semiconductor device have a variety of properties depending on the film thickness and the length thereof.
For example, a delay time with respect to a specified interconnect length was measured, with the film thickness as a parameter, for a CMOS semiconductor having gate widths of 10 xcexcm and 20 xcexcm for the N-channel transistor and the P-channel transistor, respectively, an interconnect width of 0.3 xcexcm and an interconnect interval of 0.3 xcexcm, that is, an interconnect pitch of 0.6 xcexcm. The results of the measurements were as shown in FIG. 1.
If the interconnect length is longer than a critical length, the delay time is longer for the interconnect having a thinner film thickness. Conversely, if the interconnect length is shorter than the critical length, the delay time is basically longer for the interconnect having a thicker film thickness.
Parasitic capacitances (pF/mm) for the interconnect having a thicker film thickness (0.4 xcexcm thickness) and the interconnect having a thinner film thickness (1.0 xcexcm thickness) are as shown in Table 1 by employing an index showing the number of adjacent interconnects running parallel to the subject interconnect at the minimum pitch therefrom as a parameter. The parasitic resistance is 158 xcexa9/mm for the interconnect having a film thickness of 0.4 xcexcm, and 63 xcexa9/mm for the interconnect having a film thickness of 1.0 xcexcm.
The above index is defined as follows. If two interconnects extend parallel to the subject interconnect with a minimum pitch at both sides thereof, the index is 200%. If a single interconnect extends parallel to the subject interconnect with the minimum pitch at either side thereof, it is 100%. If no interconnect extends parallel to the subject interconnect, it is 0%.
If the line widths of the interconnects in the semiconductor device are set substantially the same, a relatively large thickness is necessary for a longer-distance interconnect and a relatively small thickness is sufficient for a shorter-distance interconnect.
The interconnect constituting a critical path for the circuit operation is required to be relatively thick, and that not constituting the critical path may be relatively thin. The term xe2x80x9ccritical pathxe2x80x9d used herein is the path of an interconnect which determines the speed of operation in a chip.
Optimization of the parasitic capacitance and the parasitic resistance is required depending on the demand on the circuit operation and the interconnect length, otherwise the circuit operation is delayed.
When the short-distance interconnect and the long-distance interconnect are present in a single interconnect layer in a multi-layer structure, the film thicknesses of the two interconnects are substantially the same because they are formed in the same interconnect forming step.
In the step for forming, the optimization of the parasitic capacitance and the parasitic resistance cannot be implemented, thereby delaying the circuit operation
As an alternative process for the optimization, the layer for the short-distance interconnect and the layer for the long-distance interconnect are separately deposited and the optimization is implemented in the respective layers. In this manner, the parasitic capacitance and the parasitic resistance can be optimized in each of the interconnect layers. However, the number of the steps increases to elevate the manufacturing cost due to the layer increase, and further the interconnection structure becomes larger to be against the miniaturization of the semiconductor device.
JP-A-8(1996)-293551 describes a conventional method for forming a multi-layer interconnection structure in which top layer interconnects has a film thickness different from that of the bottom interconnect.
Referring to FIGS. 2A to 2F, the conventional method for forming the multi-layer interconnection structure described in the publication will be described.
At first, as shown in FIG. 2A, bottom interconnects 14A, 14B and 14C having substantially the same film thickness are formed on a dielectric film 12, and a first interlayer dielectric film 16 is deposited on the bottom interconnects.
The bottom interconnects 14A and 14B have small distances and have a small thickness, whereas the bottom interconnect 14C is required to be thick, which forms a lower layer of a bottom interconnect 26 (FIG. 2C) formed as the long-distance interconnect. The thickness of the first interlayer dielectric film 16 is substantially the same as that of the bottom interconnect 26.
Then, as shown in FIG. 2B, the first interlayer dielectric film 16 is etched to form via-holes 18 reaching to the bottom interconnects 14A and 14B, and an interconnect trench 20, on the bottom interconnect 14C, having the substantially same width as that of the bottom interconnect 14C.
Further, as shown in FIG. 2C, the via-holes 18 and the interconnect trench 20 are filled with the interconnect material the same as that of the bottom interconnects 14A to 14C to form via-holes 22 and an upper layer 24 of the bottom interconnect 26, respectively. The thickness of the bottom interconnect 26 is a sum of those of the bottom interconnect 14C and the upper layer 24.
Then, as shown in FIG. 2D, a second interlayer dielectric film 28 is deposited on the entire surface of the wafer and etched to form via-holes 30 reaching to the via-holes 22 or the bottom interconnect 26.
Then, as shown in FIG. 2E, an interconnect material is deposited on the entire surface of the wafer by evaporation to fill the via-holes 30 to form via-holes 32 and a top interconnect layer 34.
Thereafter, as shown in FIG. 2F, the top interconnect layer 34 is etched to form top interconnects 36 connected to the bottom interconnects 14A and 14B by way of the via-holes 22, and a top interconnect 38 connected to the bottom interconnect 26 by way of the via-hole 32, thereby providing a desired multi-layer interconnection structure.
In the above conventional method, the number of the deposition steps of the interconnect material by using an evaporation technique is two, that is, the evaporation for the bottom interconnect 14 and the via-holes 22/the upper layer of the bottom interconnect 26, and the number of the photolithographic steps of is three, that is, the patterning of the bottom interconnect 14 and opening formations for the first and the second interlayer dielectric films 16 and 28 during the formation of the bottom interconnects having the different film thicknesses. Accordingly, the conventional method includes the large number of the complicated steps.
The thick interconnect of the above configuration has the two-layered structure including the lower layer and the upper layer, and the position adjustment between the layers is difficult.
In view of the foregoing, an object of the present invention is to provide a multi-layer interconnection structure in a semiconductor device which can optimize a parasitic capacitance and a parasitic resistance depending on demands on a circuit operation and an interconnect length and the method for fabricating the same.
The present invention provides, in a first aspect thereof, a multi-layer interconnection structure in a semiconductor device including: a substrate, a first interlayer dielectric film overlying said substrate, a plurality of first interconnects embedded in said first interlevel dielectric film and each having a top surface substantially flush with a top surface of said first interlayer dielectric film; a second interlayer dielectric film formed on said first interlayer dielectric film and on said first interconnects; a plurality of second interconnects embedded in said second interlayer dielectric film, one of said second interconnects having a thickness larger than a thickness of another of said second interconnects, said one of said second interconnects having a length larger than a length of said another of said second interconnects or constituting a critical path for a circuit operation of said semiconductor device.
The present invention provides, in a second aspect thereof, a method for fabricating an interconnection structure in a semiconductor device including the steps of: forming a plurality of first interconnects embedded in a first interlayer dielectric film overlying a substrate, each of said first interconnects having a top surface substantially flush with a top surface of said first interlayer dielectric film; forming a second interlayer dielectric film having a first thickness on said first interlayer dielectric film, forming a first etch stop film on said second interlayer dielectric film at a specified location; forming a third interlayer dielectric film having a second thickness on said second interlayer dielectric film and said first etch stop film; etching said second and third interlayer dielectric films to form a first trench having a thickness substantially equal to a sum of said first thickness and said second thickness, a second trench having said second thickness, a third trench having a bottom on said etch stopper and a via-hole having said first thickness and communicated with said second trench; and forming a plurality of second interconnects by filling said first trench, said via-hole, said second trench and said third trench.
In accordance with the first and second aspects of the present invention, the semiconductor device having the multi-layer interconnection structure can be realized having the optimized parasitic capacitance and parasitic resistance depending on the demand on the circuit operation and the interconnect length. In accordance with the manufacturing method, the semiconductor device can be easily and economically obtained.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.